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Hyperstone F2-16X stone F232-Bit Flash Memory Controller Specification
PRELIMINARY
Specifications and information in this document are subject to change without notice and do not represent a commitment on the part of Hyperstone AG. Hyperstone AG reserves the right to make changes to improve functioning. Although the information in this document has been carefully reviewed, Hyperstone AG does not assume any liability arising out of the use of the product or circuit described herein. Hyperstone AG does not authorize the use of the Hyperstone microprocessor in life support applications wherein a failure or malfunction of the microprocessor may directly threaten life or cause injury. The user of the Hyperstone microprocessor in life support applications assumes all risks of such use and indemnifies Hyperstone AG against all damages. No part of this manual may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose without the permission of Hyperstone AG.
Hyperstone is a registered trademark of Hyperstone AG.
For further information please contact:
Hyperstone AG Am Seerhein 8 D-78467 Konstanz Germany Phone +49 - 7531 - 98030 Fax +49 - 7531 - 51725 E-Mail info@hyperstone.de
URL:
http://www.hyperstone.com
Copyright 1990, 2002 Hyperstone AG
Revision 08/02 FU5
TABLE OF CONTENTS
1
Table of Contents
1. Features............................................................................................................... 2 1.1. Host interface .......................................................................................... 2 1.2. Flash Memory Interface .......................................................................... 2 1.3. Controller Core ....................................................................................... 2 General Description ............................................................................................ 3 Pin Configuration................................................................................................ 5 3.1. hyperstone F2-16XN, 128-Pin Package.................................................. 5 3.2. hyperstone F2-16XT, 100-Pin Package .................................................. 8 3.3. Package Dimensions ............................................................................. 11 3.4. Bus Signals............................................................................................ 13 Functional Description...................................................................................... 18 4.1. Block Diagram ...................................................................................... 18 4.2. System Memory Map............................................................................ 18 4.3. Flash Memory Interface ........................................................................ 19 4.4. ECC Unit............................................................................................... 20 4.5. SmartMedia Unit................................................................................... 21 4.6. Reset and ROM boot............................................................................. 22 4.7. PCMCIA Interface ................................................................................ 22 4.8. Register and Sector Buffer Access Modes............................................ 32 4.9. Hyperstone Sector Buffer Access ......................................................... 35 4.10. Internal ROM ........................................................................................ 36 Electrical Specifications ................................................................................... 37 5.1. DC Characteristics ................................................................................ 37 5.2. AC Characteristics ................................................................................ 38
2. 3.
4.
5.
2
FEATURES
1. Features
1.1. Host interface

PCMCIA 2.1 and PC Card ATA standard compatible Memory mapped or I/O operation Fast ATA host-to-buffer transfer rates supporting PIO 4 in True-IDE mode Automatic sensing of PCMCIA or True-IDE host interface mode Dual integrated 512 Byte PCMCIA Sector Buffers and 256 Byte PCMCIA Attribute Memory PCMCIA Configuration Option Register, Card Configuration and Status Register and Pin Replacement Register support
1.2. Flash Memory Interface

Supports all control signal for serial type flash memory connection Supports direct connection of up to 16 (F2-16XN) or 10 (F2-16XT) flash memory chips Supports 64, 256m 512Mbit Hitachi (AND) type flash memories Supports 32, 64, 128, 256, 512Mbit, 1, 2Gbit Samsung (NAND) type flash memories Flash memory power down logic and flash memory write protect control Firmware storage in flash memory Firmware is loaded into internal memory by the boot ROM Error Correcting Code capable of correcting 6 bytes in a 512 byte sector On-chip voltage regulator for 3.3V flash memory power supply On-chip voltage regulator for 2.5V processor core power supply
1.3. Controller Core

High performance microprocessor core based on the Hyperstone architecture Clock frequency 20MHz or 40MHz using R-C oscillator 8 Kbyte Internal Boot ROM 16 Kbyte internal RAM Automatic power-down mode during wait periods for host data or flash memory operation completion Automatic sleep mode during host inactivity periods, Icc < 200 A 128 pin LQFP (14x14x1.4 mm, F2-16XN), 100 pin TQFP (14x14x1.0 mm, F2-16XT) 0.25 m CMOS technology Supply voltage 5.0V 10% or 3.3V 5%
GENERAL DESCRIPTION
3
2. General Description
The Hyperstone F2-16XN and F2-16XT flash memory controllers are among the most powerful single-chip controllers on the market for designing ATA based Flash Memory PC Cards / CompactFlash Cards. The required external component count is reduced to a bare minimum of few passive components enabling the design of very low-cost but highperformance ATA flash memory cards / CompactFlash Cards. The Hyperstone F2-16X flash memory controller can operate with flash memory devices from Hitachi and Samsung or compatible chips thereof. It operates with 5.0V and 3.3V and enables automatic voltage detection for the cards. A highly sophisticated Error Correction Code and a wear-leveling algorithm are also implemented. A complete set of development tools is available which enables you to design ATA Flash Memory Cards / CompactFlash Cards with a very competitive cost/performance ratio. The main features of Hyperstone F2-16X flash memory controller are:

Inexpensive single-chip controller for ATA flash memory cards / CompactFlash cards Full support for Hitachi (AND) and Samsung (NAND) flash memories Built-in 3.3V voltage regulator for flash memory supply Built-in 2.5V voltage regulator for processor core supply Built-in PC card / CompactFlash Interface Data transfer rate to flash memories: up to 20 MBytes/s Supports True-IDE mode On-chip ECC unit Sophisticated software for wear leveling Automatic power-down mode and sleep mode Small 128-pin LQFP package (F2-16XN) available in a 100-pin TQFP package (F2-16XT) for low-cost CompactFlash Card applications supporting up to 10 flash memory chips Comprehensive equipment available for development and test of hardware and firmware
The Hyperstone F2-16X single-chip controller for ATA Flash Memory Cards / CompactFlash Cards is based on the Hyperstone E1-32X microprocessor core providing a modern 32-bit RISC architecture. The controller's flash memory interface allows the direct connection of up to 16 flash memory chips (10 chips for the F2-16XT) and supports either Hitachi 64, 256, 512 Mbit flash memories (e.g. HN29W6411) or Samsung type flash memories (32 Mbit to 2 Gbit). Next-generation flash memories will be supported as well. Through the sophisticated memory interface of the Hyperstone F2-16X, your flash memory card will achieve a superior performance with a data transfer rate to flash memories of up to 20 MBytes/s. An on-chip ECC unit generates the required code bytes for error detection and correction of up to six bytes per 512 Byte data sector. Code byte generation during write operations as well as error detection during read operation is implemented on the fly without any speed penalties.
4
GENERAL DESCRIPTION
The controller is equipped with 16 KByte internal memory that is used for storage of code and data. The internal memory can also be used as an intermediate memory for storing data blocks during a wear-leveling procedure. The Hyperstone F2-16X controller works at power supply voltages of 5.0V as well as 3.3V. It provides a built-in voltage regulator of 3.3V to supply flash memories with the required voltage even when the interface from the host offers just a voltage of 5.0V. An 8 KByte internal boot ROM includes basic routines for accessing the flash memories and for loading the main code into the internal memory of the Hyperstone F2-16X. This boot concept offers a high degree of flexibility while keeping the component count small. The PC Card / CompactFlash interface provides all required signals and is fully compliant with the PC Card standard Rel. 2.1. The PC Card controller part of the Hyperstone F2-16X includes 256 Byte attribute memory, PCMCIA configuration and status registers, two 512 Byte sector buffers and the complete ATA register set. Optionally, the controller can be operated in True-IDE mode. A comprehensive tool kit is also available for developing and testing ATA Flash Memory Cards / CompactFlash Cards based on Hyperstone F2-16X. This includes a HW/SW test environment, pre-format HW/SW, Firmware for ECC and wear leveling.
PIN CONFIGURATION
5
3. Pin Configuration
3.1. hyperstone F2-16XN, 128-Pin Package
3.1.1. Pin Configuration - View from Top Side
D7 D0 A8 OE# VCC_F A7 A6 A5 GND_F GND_F A4 A3 A2 IOWR# IORD# PD10 PIOIS16# A0 A1 PD9 PD2 PD8 VCC_P PD1 PSTSCHG# INT4 PD0 PSPKR# GND_P PA0 PREG# PA1
97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
D1 D6 WE2# FOE# FWE# GND_F XTALI XTALC XTALR D2 D5 WE3# D3 D4 FRDY VCC_C VCC_C GND_C GND_C FRES# FHOE# VCC_F WE# CS3# CS1# D11 D12 D10 D13 D9 D14 D8
hyFlash F2-16XN
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
GND_F GND_F RESET# D15 A13 A12 VCC_F A11 A10 A9 COUT CADJ VCC_R GND_R VCC_R VCC_R FADJ FOUT FOUT PD3 BUSRQ# A14 PD11 PD4 PD12 VCC_P PD5 PD13 PD6 PD14 GND_P GND_P
Figure 1: Hyperstone F2-16XN, 128 Pin LQFP Package
PINPACK# PA2 PWAIT# A19 A18 A17 PA3 PRESET# PA4 PA5 PCSEL# PA6 VCC_P GND_P PIREQ# PA7 PWE# PA8 VCC_C GND_C GND_C PIOWR# PA9 PIORD# A16 A15 POE# PA10 PCE2# PCE1# PD15 PD7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
6
PIN CONFIGURATION
3.1.2. Pin Cross Reference by Pin Name
Signal Location Signal Location Signal Location Signal Location
A0....................114 A1....................115 A10....................56 A11....................57 A12....................59 A13....................60 A14....................43 A15....................26 A16....................25 A17......................6 A18......................5 A19......................4 A2....................109 A3....................108 A4....................107 A5....................104 A6....................103 A7....................102 A8......................99 A9......................55 BUSRQ# ...........44 CADJ.................53 COUT ................54 CS1# .................72 CS3# .................73 D0......................98 D1......................96 D10....................69 D11....................71 D12....................70 D13....................68 D14....................66
D15 ...................61 D2 .....................87 D3 .....................84 D4 .....................83 D5 .....................86 D6 .....................95 D7 .....................97 D8 .....................65 D9 .....................67 FADJ .................48 FHOE# ..............76 FOE#.................93 FOUT ................46 FOUT ................47 FRDY ................82 FRES# ..............77 FEW#................92 GND_C .............20 GND_C .............21 GND_C .............78 GND_C .............79 GND_F..............63 GND_F..............64 GND_F..............91 GND_F............105 GND_F............106 GND_P..............14 GND_P..............33 GND_P..............34 GND_P............125 GND_R .............51 INT4 ................122
IORD# .............111 IOWR# ............110 OE#.................100 PA0 .................126 PA1 .................128 PA10 .................28 PA2 .....................2 PA3 .....................7 PA4 .....................9 PA5 ...................10 PA6 ...................12 PA7 ...................16 PA8 ...................18 PA9 ...................23 PCE1#...............30 PCE2#...............29 PCSEL# ............11 PD0 .................123 PD1 .................120 PD10 ...............112 PD11 .................42 PD12 .................40 PD13 .................37 PD14 .................35 PD15 .................31 PD2 .................117 PD3 ...................45 PD4 ...................41 PD5 ...................38 PD6 ...................36 PD7 ...................32 PD8 .................118
PD9 ................. 116 PINPACK# .......... 1 PIOIS16# ........ 113 PIORD# ............ 24 PIOWR# ........... 22 PIREQ#............. 15 POE# ................ 27 PREG#............ 127 PRESET# ........... 8 PSPKR#.......... 124 PSTSCHG# .... 121 PWE#................ 17 PWAIT# .............. 3 RESET#............ 62 VCC_C.............. 19 VCC_C.............. 80 VCC_C.............. 81 VCC_F .............. 58 VCC_F .............. 75 VCC_F ............ 101 VCC_P .............. 13 VCC_P .............. 39 VCC_P ............ 119 VCC_R.............. 49 VCC_R.............. 50 VCC_R.............. 52 WE# .................. 74 WE2# ................ 94 WE3# ................ 85 XTALC .............. 89 XTALI................ 90 XTALR .............. 88
PIN CONFIGURATION
7
3.1.3. Pin Cross Reference by Location
Location Signal Location Signal Location Signal Location Signal
1 .......... PINPACK# 2 ..................... PA2 3 .................PWIT# 4 ..................... A19 5 ..................... A18 6 ..................... A17 7 ..................... PA3 8 ........... PRESET# 9 ..................... PA4 10 ................... PA5 11 ............ PCSEL# 12 ................... PA6 13 ..............VCC_P 14 ............. GND_P 15 .............PIREQ# 16 ................... PA7 17 ............... PWE# 18 ................... PA8 19 ..............VCC_C 20 ............. GND_C 21 ............. GND_C 22 ........... PIOWR# 23 ................... PA9 24 ............ PIORD# 25 ................... A16 26 ................... A15 27 ................ POE# 28 ................. PA10 29 .............. PCE2# 30 .............. PCE1# 31 .................PD15 32 ...................PD7
33 ............. GND_P 34 ............. GND_P 35 ................. PD14 36 ................... PD6 37 ................. PD13 38 ................... PD5 39 .............. VCC_P 40 ................. PD12 41 ................... PD4 42 ................. PD11 43 ....................A14 44 ........... BUSRQ# 45 ................... PD3 46 ................ FOUT 47 ................ FOUT 48 .................FADJ 49 ..............VCC_R 50 ..............VCC_R 51 ............. GND_R 52 ..............VCC_R 53 ................ CADJ 54 ................COUT 55 ......................A9 56 ....................A10 57 ....................A11 58 .............. VCC_F 59 ....................A12 60 ....................A13 61 ................... D15 62 ............RESET# 63 ..............GND_F 64 ..............GND_F
65..................... D8 66................... D14 67..................... D9 68................... D13 69................... D10 70................... D12 71................... D11 72................. CS1# 73................. CS3# 74.................. WE# 75.............. VCC_F 76.............. FHOE# 77.............. FRES# 78............. GND_C 79............. GND_C 80..............VCC_C 81..............VCC_C 82................ FRDY 83..................... D4 84..................... D3 85................ WE3# 86..................... D5 87..................... D2 88.............. XTALR 89.............. XTALC 90................ XTALI 91..............GND_F 92................FWE# 93.................FOE# 94................ WE2# 95..................... D6 96..................... D1
97..................... D7 98..................... D0 99......................A8 100.................OE# 101............ VCC_F 102....................A7 103....................A6 104....................A5 105............GND_F 106............GND_F 107....................A4 108....................A3 109....................A2 110............ IOWR# 111............. IORD# 112............... PD10 113........ PIOIS16# 114....................A0 115....................A1 116................. PD9 117................. PD2 118................. PD8 119............ VCC_P 120................. PD1 121.....PSTSCHG# 122................ INT4 123................. PD0 124.......... PSPKR# 125............GND_P 126................. PA0 127............PREG# 128................. PA1
8
PIN CONFIGURATION
3.2. hyperstone F2-16XT, 100-Pin Package
3.2.1. Pin Configuration - View from Top Side
D7 D0 A8 VCC_F A7 A6 A5 GND_F A4 A3 A2 PD10 PIOIS16# PD9 PD2 PD8 VCC_P PD1 PSTSCHG# PD0 PSPKR# GND_P PA0 PREG# PA1
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
D1 D6 FOE# FWE# GND_F XTALI XTALC XTALR D2 D5 D3 D4 FRDY VCC_C GND_C FRES# FHOE# VCC_F D11 D12 D10 D13 D9 D14 D8
hyFlash F2-16XT
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
GND_F RESET# D15 A13 A12 A11 A10 A9 COUT CADJ VCC_R GND_R VCC_R FADJ FOUT PD3 PD11 PD4 PD12 VCC_P PD5 PD13 PD6 PD14 GND_P
Figure 2: Hyperstone F2-16XT, 100 Pin TQFP Package
PINPACK# PA2 PWAIT# PA3 PRESET# PA4 PA5 PCSEL# PA6 GND_P PIREQ# PA7 PWE# PA8 VCC_C GND_C PIOWR# PA9 PIORD# POE# PA10 PCE2# PCE1# PD15 PD7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
PIN CONFIGURATION
9
3.2.2. Pin Cross Reference by Pin Name
Signal Location Signal Location Signal Location Signal Location
A10....................44 A11....................45 A12....................46 A13....................47 A2......................86 A3......................85 A4......................84 A5......................82 A6......................81 A7......................80 A8......................78 A9......................43 CADJ.................41 COUT................42 D0 .....................77 D1 .....................75 D10 ...................55 D11 ...................57 D12 ...................56 D13 ...................54 D14 ...................52 D15 ...................48 D2 .....................67 D3 .....................65 D4 .....................64
D5 ..................... 66 D6 ..................... 74 D7 ..................... 76 D8 ..................... 51 D9 ..................... 53 FADJ ................. 37 FHOE# .............. 59 FOE#................. 73 FOUT ................ 36 FRDY ................ 63 FRES# .............. 60 FWE#................ 72 GND_C ............. 16 GND_C ............. 61 GND_F.............. 50 GND_F.............. 71 GND_F.............. 83 GND_P.............. 10 GND_P.............. 26 GND_P.............. 97 GND_R ............. 39 PA0 ................... 98 PA1 ................. 100 PA10 ................. 21 PA2 ..................... 2
PA3 ..................... 4 PA4 ..................... 6 PA5 ..................... 7 PA6 ..................... 9 PA7 ................... 12 PA8 ................... 14 PA9 ................... 18 PCE1# .............. 23 PCE2# .............. 22 PCSEL# .............. 8 PD0................... 95 PD1................... 93 PD10................. 87 PD11................. 34 PD12................. 32 PD13................. 29 PD14................. 27 PD15................. 24 PD2................... 90 PD3................... 35 PD4................... 33 PD5................... 30 PD6................... 28 PD7................... 25 PD8................... 91
PD9................... 89 PINPACK# .......... 1 PIOIS16# .......... 88 PIORD# ............ 19 PIOWR# ........... 17 PIREQ#............. 11 POE# ................ 20 PREG#.............. 99 PRESET# ........... 5 PSPKR#............ 96 PSTSCHG# ...... 94 PWAIT# .............. 3 PWE# ............... 13 RESET#............ 49 VCC_C.............. 15 VCC_C.............. 62 VCC_F .............. 58 VCC_F .............. 79 VCC_P.............. 31 VCC_P.............. 92 VCC_R.............. 38 VCC_R.............. 40 XTALC .............. 69 XTALI................ 70 XTALR .............. 68
10
PIN CONFIGURATION
3.2.3. Pin Cross Reference by Location
Location Signal Location Signal Location Signal Location Signal
1 .......... PINPACK# 2 ..................... PA2 3 .............. PWAIT# 4 ..................... PA3 5 ........... PRESET# 6 ..................... PA4 7 ..................... PA5 8 .............. PCSEL# 9 ..................... PA6 10 ............. GND_P 11 ............ PIREQ# 12 ................... PA7 13 ............... PWE# 14 ................... PA8 15 ............. VCC_C 16 ............. GND_C 17 ........... PIOWR# 18 ................... PA9 19 ............ PIORD# 20 ................ POE# 21 ................. PA10 22 .............. PCE2# 23 .............. PCE1# 24 .................PD15 25 ...................PD7
26 ............. GND_P 27 .................PD14 28 ...................PD6 29 .................PD13 30 ...................PD5 31 ..............VCC_P 32 .................PD12 33 ...................PD4 34 .................PD11 35 ...................PD3 36 ................FOUT 37 .................FADJ 38 ..............VCC_R 39 ............. GND_R 40 ..............VCC_R 41 ................ CADJ 42 ............... COUT 43 ..................... A9 44 ................... A10 45 ................... A11 46 ................... A12 47 ................... A13 48 ................... D15 49 ............RESET# 50 ..............GND_F
51 ..................... D8 52 ................... D14 53 ..................... D9 54 ................... D13 55 ................... D10 56 ................... D12 57 ................... D11 58 .............. VCC_F 59 ..............FHOE# 60 .............. FRES# 61 ............. GND_C 62 ..............VCC_C 63 ................ FRDY 64 ..................... D4 65 ..................... D3 66 ..................... D5 67 ..................... D2 68 .............. XTALR 69 .............. XTALC 70 ................XTALI 71 ..............GND_F 72 ................FWE# 73 ................ FOE# 74 ..................... D6 75 ..................... D1
76 ..................... D7 77 ..................... D0 78 ......................A8 79 .............. VCC_F 80 ......................A7 81 ......................A6 82 ......................A5 83 ..............GND_F 84 ......................A4 85 ......................A3 86 ......................A2 87 ................. PD10 88 .......... PIOIS16# 89 ................... PD9 90 ................... PD2 91 ................... PD8 92 .............. VCC_P 93 ................... PD1 94 ...... PSTSCHG# 95 ................... PD0 96 ............PSPKR# 97 ..............GND_P 98 ................... PA0 99 ..............PREG# 100 ................. PA1
PIN CONFIGURATION
11
3.3. Package Dimensions
D D1
E1 Index e b A1 A2 L
Figure 3: Hyperstone F2-16X Package Outline Symbol A1 A2 E, D E1, D1 L e B Term Standoff height Package height Overall length & width Package length & width Lead footprint Lead pitch Lead width Definition Height of package itself Length and width including leads Length and width of package Length of flat lead section Lead pitch Width of a lead
Height from ground plane to bottom edge of package
E
12
PIN CONFIGURATION
Hyperstone F2-16XN, 128 Pin LQFP Package
Symbol Dimensions in Millimeters Min. A1 A2 E, D E1, D1 L B e 0.05 1.35 15.80 13.00 0.45 0.13 Nom. 0.10 1.40 16.00 14.00 0.60 0.18 0.40 Max. 0.15 1.45 16.20 14.10 0.75 0.23 Dimensions in Inches Min. .002 .053 .622 .547 .018 .005 Nom. .004 .055 .630 .551 .024 .007 .0157 Max .006 .057 .638 .555 .030 .009
Hyperstone F2-16XT, 100 Pin TQFP Package
Symbol Dimensions in Millimeters Min. A1 A2 E, D E1, D1 L B e 0.05 0.95 15.80 13.00 0.45 0.17 Nom. 0.10 1.00 16.00 14.00 0.60 0.22 0.50 Max. 0.15 1.05 16.20 14.10 0.75 0.27 Dimensions in Inches Min. .002 .037 .622 .547 .018 .007 Nom. .004 .039 .630 .551 .024 .009 .0197 Max .006 .041 .638 .555 .030 .011
PIN CONFIGURATION
13
3.4. Bus Signals
3.4.1. Bus Signals for the F2-16X Flash Memory Controller The following table is an overview of the bus signals of the Hyperstone F2-16X flash memory controller. The signal states are defined as I = input, O = output, pu = pull-up, pd = pull-down, h = hold and s = strong.
Status Pins Pins Signal Name F2-16XN F2-16XT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 16 1 1 1 1 1 1 FWE# FOE#/FSC FRDY FRES# FHOE# FOUT FADJ COUT CADJ PCE1# PCE2# PREG# PWE# POE# PIOWR# PIORD# PCSEL# PRESET PA(10..0) PD(15..0) PIOIS16# PINPACK# PIREQ# PSTSCHG# PSPKR# PWAIT# Description
Flash Memory Control O O I/pu/s O/pd O/pu O I I I I/pu I/pu I/h I/pu I/pu I/pu I/pu I/pu I/h I/h I/O/h O O O/pu O/pu O/pu O/pu Samsung/Hitachi Write Enable Samsung Output Enable, Hitachi Clock Flash Ready/Busy (E1-32X IO1) Flash Reset/Write Protect (E1-32X IO2) Hitachi Output Enable (E1-32X IO3) 3.3V Flash Power Supply Output External Resistor for 3.3V Voltage Adjustment 2.5V Core Power Supply Output External Resistor for 2.5V Voltage Adjustment PC Card Interface Card Enable 1 Card Enable 2 Attribute Memory or I/O Enable Memory Write Enable, Service Mode Memory Output Enable, True-IDE Mode Select I/O Write Enable I/O Read Enable True-IDE Chip Select Reset Signal Address Bus Data Bus Write Protect / 16-bit I/O Transfer Input Acknowledge Ready/Busy / Interrupt Request Status Change / True-IDE DIAG Speaker / DMA Request / True-IDE DASP Wait Signal
Flash Memory and Core Voltage Supply
14
PIN CONFIGURATION
States
Pins Pins Signal Name F2-16XN F2-16XT 8 12 16 1 1 1 2 1 1 1 1 1 1 1 1 1 2 3 4 3 2 4 5 4 12 16 1 1 1 1 1 2 3 2 1 3 3 2 100 A(19..14,1..0) A(13..2) D(15..0) BUSRQ# CS3# CS1# WE2#, WE3# WE# OE# IOWR# IORD# INT4 RESET# XTALI XTALC XTALR VCC_R VCC_P VCC_F VCC_C GND_R GND_P GND_F GND_C
Description
General Control O O I/O O O O O O O O O I/pd I I O O Address Bus Address Bus Data Bus Multiple Controller Bus Request Chip Select for MEM3 (for Debug) Chip Select for MEM1 (for Debug) SRAM Write Byte Enable (for Debug) SRAM Write Enable (for Debug) Output Enable (for Debug) I/O Write Enable (for Debug) I/O Read Enable (for Debug) Interrupt 4, Boot Select ROM / MEM3 (for Debug) Reset R-C Oscillator Input Capacitor Resistor Power Supply Power Supply Voltage, Regulator Power Supply Voltage, PCMCIA Bus Power Supply Voltage, Flash Memory Power Supply Voltage, Core Ground, Regulator Ground, PCMCIA Bus Ground, Flash Memory Ground, Core
Total:
128
Table 1: Bus Signals for the F2-16X Flash Memory Controller
PIN CONFIGURATION
15
3.4.2. Bus Signal Description The following section describes the bus signals for both the Hyperstone F2-16X controller in detail. In the following signal description, the signal states are defined as I = input, O = output, U = pull-up, D = pull-down. I XTALI R/C Clock Oscillator Input. This input connects to the other side of the resisors and the capacitor connected to XTALR1, XTALR2 and XTALC. Connect a 22pF capacitor from this pin to ground. R/C Clock Oscillator Capacitor Output. Connect a 22pF capacitor between this pin and XTALI. R/C Clock Oscillator Resistor Output. The resistor connected between this pin and XTALI determines the operating clock frequency. Use a 470 resistor to obtain a frequency of about 20 MHz. The address bits A19..A0 represent the address bus. An active high bit signals a "one". A0 is the least significant bit. The address pins are used as chip select signals for up to 12 Flash memory chips and to address an external SRAM or ROM memory. The A19..A14 and A1..A0 signals are not available on the F2-16XT. Address bits A13..A9 can be used as Flash memory "Ready" interrupt inputs by enabling this functionality in FCR if they are not used as chip select outputs. Data bus. The signals D15..D0 represent the bidirectional data bus; active high signals a "one". At a read access, data is transferred from the data bus to the register set or to the instruction cache only at the cycle corresponding to the last actual read access cycle, thus inhibiting garbled data from being transferred. At a write access, the data bus signals are activated during the address setup, write and bus hold cycle(s). If byte wide Flash memory chips are used, they are connected to the D0..D7 data lines. Multiple Controller Bus Request. This pin is used for the communication between multiple controllers connected to the PCMCIA bus. Chip Select. Chip select is signaled in the same cycle(s) as the address signals. Active low of CS1# or CS3# indicates chip select for the memory areas MEM1 (SRAM) and MEM3 (ROM) respectively. These signals are not available on the F2-16XT. SRAM Write Enable. Active low indicates a write access to SRAM. This signal is not available on the F2-16XT.
O O
XTALC XTALR1
O
A19..A0
O/I
D15..D0
O
BUSRQ#
O
CS1#, CS3#
O
WE#
16
PIN CONFIGURATION
3.4.2. Bus Signal Description (continued) States Names O WE2#, WE3# Use SRAM Write Byte Enable. Active low indicates write enable for the byte on D0..D7 (WE3#), or D8..D15 (WE2#), active high indicates write disable. These signals are not available on the F216XT.
O
OE#
Output Enable for SRAMs or ROMs. OE# is active low on a SRAM or ROM read access. This signal is not available on the
F2-16XT.
O O I,D
IORD# IOWR# INT4
I/O Read Strobe. IORD# is low on I/O read access cycles, high on all other cycles. This signal is not available on the F2-16XT. I/O Write Strobe. IOWR# is active low on I/O write access cycles. This signal is not available on the F2-16XT. Interrupt Request and Boot select. A signal of a specified level on the INT4 interrupt request pins causes an interrupt exception when the interrupt lock flag L is zero and the corresponding INT4Mask bit in FCR is not set. The INT4Polarity bit in FCR specifies the level of the INT4 signal: INT4Polarity = 1 causes an interrupt on a high input signal level, INT4Polarity = 0 causes an interrupt on a low input signal level. INT4 may be signaled asynchronously to the clock; they are not stored internally. The INT4 pin is normally reserved for the hyICE debug connection. Additionally, the INT4 state on a reset exception determines the location of the reset boot procedure. If INT4 is low on reset, the F2-16X begins booting from the internal ROM, if INT4 is high on reset, the F2-16X begins booting from the external MEM3 ROM. This signal is not available on the F2-16XT. Reset processor. RESET# low resets the processor to the initial state and halts all activity. RESET# must be low for at least one cycle. On a transition from low to high, a Reset exception occurs and the processor starts execution at the Reset entry determined by the INT4 state. The transition may occur asynchronously to the clock. We recommend connecting this pin to a voltage monitoring circuit with open-drain output (e.g. Torex XC61A) supplying a reset signal for supply voltages less than 2.6 or 2.7V, connected to a R/C combination of 100 k and 100 nF giving an additional reset delay in the order of 10 ms. If no voltage monitoring chip is used, the R/C reset delay should be in the range of about 200 ms, for example with 1 M and 220 nF. 3.3V Flash Memory Power Supply. This output provides a regulated 3.3V supply if the F2-16X power supply voltage is above 3.3V. This supply voltage must also be connected to the VCC_F pins.
I
RESET#
O
FOUT
PIN CONFIGURATION
17
3.4.2. Bus Signal Description (continued) States Names I FADJ Use 3.3V Flash Memory Power Supply Adjustment. Connect a * k resistor from this pin to GND, and a * k resistor from this pin to FOUT. 2.5V Core Power Supply. This output provides a regulated 2.5V supply if the F2-16X power supply voltage is above 3.3V. This supply voltage must be connected to the VCC_C pins. 2.5V Core Power Supply Adjustment. Connect a * k resistor from this pin to GND, and a * k resistor from this pin to COUT. PCMCIA Card Enable 1 PCMCIA Card Enable 2 PCMCIA Attribute Memory or I/O Enable PCMCIA Memory Write Enable, Service Mode select (see Boot ROM description) PCMCIA Output Enable, True-IDE Mode select PCMCIA I/O Write Enable PCMCIA I/O Read Enable True-IDE Master/Slave select PCMCIA Reset signal. This pin includes an input filter that filters pulses shorter than about 40 ns. PCMCIA Address Bus PCMCIA Data Bus PCMCIA Write Protect / I/O is 16 bit signal PCMCIA Input Achnowledge PCMCIA Ready/Busy signal / Interrupt Request PCMCIA Status Change / True-IDE DIAG PCMCIA Speaker / True-IDE DASP Samsung and Hitachi Flash Memory Write Enable. Connect to the Samsung or Hitachi WE# pin. Samsung Output Enable, Hitachi Bus Clock signal. Connect to Samsung RE# or Hitachi SC pin. Samsung and Hitachi Flash Ready/Busy signal. Samsung and Hitachi Flash Write Protect/Reset signal. Connect to the Samsung WP# or Hitachi RES# pin. Flash memory type select and Hitachi output enable signal. Connect to ground for Samsung flashes, connect to the Hitachi OE# signal for Hitachi flashes.
O
COUT
I
CADJ
I,U I,U I I,U I,U I,U I,U I,U I I I/O O O O,U O,U O,U O O I,U O,D O,U
PCE1# PCE2# PREG# PWE# POE# PIOWR# PIORD# PCSEL# PRESET PA(10..0) PD(15..0) PIOIS16# PINPACK# PIREQ# PSTSCHG# PSPKR# FWE# FOE#/FSC FRDY FRES# FHOE#
18
FUNCTIONAL DESCRIPTION
4. Functional Description
4.1. Block Diagram
4.2. System Memory Map
The processor provides on-chip all functions for controlling memory and peripheral devices. The number of bus cycles used for a memory or I/O access is also defined by the processor, thus, no external bus controllers are required. All memory and peripheral devices can be connected directly, pin by pin, without any glue logic. The memory address space is divided into six partitions as follows:
Address (Hex) 4000 0000..7FFF FFFF 8000 0000..BFFF FFFF C000 0000..C7FF FFFF C800 0000..CFFF FFFF D000 0000..DFFF FFFF E000 0000..FFFF FFFF Address Space MEM1 MEM2 IRAM IRAM IROM MEM3 Memory Type external SRAM external Flash Memory Internal RAM Sector Buffers, Attribute Memory Internal Boot ROM external ROM
FUNCTIONAL DESCRIPTION
19
Access to the registers of the PCMCIA and flash memory interface takes place in the processor's I/O address space.
4.3. Flash Memory Interface
Samsung type or Hitachi type flash memory chips are connected to the Hyperstone F2-16X as described below. 4.3.1. Samsung KM29N32000TS (or similar)
Samsung KM29N32000TS CLE ALE CE# WE# RE# SE# I/O 0 ... I/O 7 (I/O 15) WP# Ready/Busy# F2-16X A2 A3 one of A19..A4 FWE# FOE#/FSC GND D0 ... D7 (D15) FRES# FRDY
The FHOE# pin is grounded externally to indicate that Samsung flash memory is connected. In order to avoid static current flowing through the FHOE# pull-up resistor, the FHOE# pin should be switched to output driving 0 when the low state of FHOE# is detected. When a Samsung flash memory chip is connected, the FCR bit 7 must remain set in the default reset state (1). Switching this bit to 0 with a Samsung flash memory chip connected may cause a collision on the Hyperstone F2-16X data bus. The FWE# and FOE# control signals are activated on any MEM2 write or read access when address bit A22 is set to zero. Address lines A19 to A2 are used for control signal and chip select generation. Address bits A1 to A0 should not be connected and should be zero on a MEM2 access so that word accesses are possible. Setting A22 to one on a MEM2 write or read access inhibits the generation of the FWE# and FOE# signals. This mode may be used to pre-set the address or data lines to a specific value without causing an actual access. At most 16 Samsung flash chips can be connected to the Hyperstone F2-16X. Since address bit A2 is used as CLE, double-word flash accesses are not possible. Flash chip 0 CE# is A4, chip 1 CE# is A5, ... chip 15 CE# is A19.
20
FUNCTIONAL DESCRIPTION
4.3.2. Hitachi HN29W6411 (or similar)
Hitachi HN29W6411 CDE# CE# WE# SC OE# I/O 0 ... I/O 7 RES# RDY/Busy# F2-16X A3 one of A19..A4 FWE# FOE#/FSC FHOE# D0 ... D7 FRES# FRDY
The FHOE# pin is connected to the OE# pin of the Hitachi flash memory chip. The FHOE# pin sets the OE# signal to high via a pull-up resistor. This logic level can be used to indicate that a Hitachi flash memory chip is connected. The FHOE# pin should be switched to output driving 1 when the high state of FHOE# is detected. Bit 7 in FCR should be set to 0 enabling the Hitachi control signals on FWE# and FOE#/FSC pins when a high state at FHOE# is detected. This should be done before the FRES# pin is brought high. The FWE# control signal is activated on a MEM2 write access when A21 = 0 and A22 = 0. In order to meet the timing requirements, these accesses must be performed with a minimum of 2 access cycles at 16 MHz or 3 access cycles at 18 MHz. The OE# signal must be high during these accesses. The FSC control signal is activated on a MEM2 read or write access when A21 = 1 and A22 = 0. For these accesses, a single-cycle access time is allowed up to a clock frequency of 18 MHz. Before a write access, the FHOE# signal must be brought high, for a read access, the FHOE# signal must be brought low before the accesses and back high after the accesses. Setting A22 to one on a MEM2 write or read access inhibits the generation of the FWE# and FSC signals. This mode may be used to pre-set the address or data lines to a specific value without causing an actual access. At most 16 Hitachi flash chips can be connected to the Hyperstone F2-16X. Flash chip 0 CE# is A4, chip 1 CE# is A5, ... chip 15 CE# is A19.
4.4. ECC Unit
The ECC unit consists of the Parity Unit (parity byte generation) and the Syndrome Unit (syndrome byte computation). This unit implements a Reed-Solomon ECC that is able to correct two bytes in an ECC block. The maximum ECC block length is 251 bytes. The parity unit listens to MEM2 write accesses when A20 = 1 and processes the byte present on the output data lines. The syndrome unit listens to MEM2 read accesses when A20 = 1 and processes the byte present on the read data lines. The parity and syndrome units process one byte per clock cycle. When the MEM2 bus width is 16 bit, the MEM2
FUNCTIONAL DESCRIPTION
21
access time must be at least 2 clock cycles to give the time to process both bytes of a MEM2 access. In this case, data bits 15..8 are processed first, then data bits 7..0. The generated parity bytes b3..b0 and the generated syndrome bytes s3..s0 can be read from the ECC unit using the I/O interface. The ECC unit responds to internal I/O accesses (A27 = 1) when A22 = 1. There is an 8 bit down counter register associated with the syndrome unit. Whenever bytes are sent to the syndrome unit (on a MEM2 read with A20 = 1) the counter is decremented by one for each byte that is equal to FF16. This counter register can be used to check the number of non-erased (value not equal to FF16) bytes in a data block.
A16 0 0 0 0 0 0 0 0 0 0 0 A15 0 0 0 0 0 0 0 1 1 1 1 A14 0 0 1 1 0 1 1 0 0 0 1 A13 0 1 0 1 x 0 1 0 0 1 1 R/W Description R R R R W W W W R W W read 16 bit parity bytes b2, b3 read 16 bit parity bytes b0, b1 read 16 bit syndrome bytes s3, s2 read 16 bit syndrome bytes s1, s0 reset parity bytes b3 ... b0 to zero write 16 bit syndrome bytes s3, s2 write 16 bit syndrome bytes s1, s0 write 8 bit down counter register read 8 bit down counter register write 8 bit data into parity unit (for test) write 8 bit data into syndrome unit (for test)
4.5. SmartMedia Unit
The SmartMedia Unit computes the Line Parity and Column Parity information of the SmartMedia ECC for a data block of up to 256 bytes according to the SmartMedia Physical Format Specification. The SmartMedia unit listens to MEM2 read or write accesses when A24 = 1 and processes the byte present on the read or write data lines. The SmartMedia unit processes one or two bytes per clock cycle, depending on the MEM2 bus width. The generated line and column parity bytes can be read from the SmartMedia unit using the I/O interface. The SmartMedia unit responds to internal I/O accesses (A27 = 1) when A22 = 1.
A16 A15 A14 A13 R/W Description 1 1 1 1 1 1 0 0 0 1 1 1 0 0 0 0 0 1 0 1 x 0 1 0 R R W read even Line Parity and Column Parity read odd Line Parity and Column Parity reset Line Parity and Column Parity to 1, reset byte counter
R/W read/write Line Parity LP(7..0) R/W read/write Line Parity LP(15..8) R/W read/write Column Parity CP(5..0)
22
FUNCTIONAL DESCRIPTION
The bit arrangements are the following:
A16 A15 A14 A13 R/W Data Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Line Parity 1 1 1 0 0 0 0 0 0 0 1 x R R W zero zero 14 12 10 15 13 11 8 9 6 7 4 5 2 3 0 1
Column P 4 5 2 3 0 1
don't care Line Parity
1 1
1 1
0 0
0 1
R/W R/W
zero zero
7
6
5
4
3
2
1 9
0 8
15 14 13 12 11 10 Column Parity
1
1
1
0
R/W
zero
5
4
3
2
1
0
one
4.6. Reset and ROM boot
The Hyperstone F2-16XN uses the INT4 line state at reset to select between booting from internal boot ROM and booting from external MEM3. The INT4 pad has an internal pulldown resistor so that INT4 is low when INT4 is not connected. If the INT4 line is high at reset (connected to the interrupt line of the hyICE), the Hyperstone F2-16XN reset begins fetching instructions from MEM3 address FFFF FFF816. If the INT4 line is low at reset (no hyICE connected), the F2-16XN begins booting from its internal boot ROM. The F2-16XT does not have the INT4 pin so it always boots from the internal boot ROM. If the Hyperstone F2-16XN should boot from the internal boot ROM with the hyICE connected (for example to have the two LEDs available), the hyICE's interrupt line must be disconnected from the INT4 pin by pulling the corresponding jumper on the hyICE.
4.7. PCMCIA Interface
The register model of the Hyperstone F2-16X PCMCIA consists of three groups of registers: the F2-16X only registers, the PCMCIA configuration registers and the ATA register file. The F2-16X PCMCIA interface responds to internal I/O accesses (A27 = 1) when A25 = 0. The F2-16X address mapping together with the read/write status of the registers when accessed by the Hyperstone F2-16X or the PCMCIA host in the Busy or Not Busy state is given in the following table:
FUNCTIONAL DESCRIPTION
23
A24 A23 A16 A15 A14 A13 Reg 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ISR MSR TIR PIR C1 C2 C3 C4 A01 A02 A03 A04 A05 A06 A07 A00 A08 A10 A09
Busy hy PC R/W R/W R/W W R/W R/W R/W R/W R R R R
Not Busy hy PC R/W R/W R/W W R R R R -
Description Interrupt Status Register Mode and Control Register True-IDE Mode Register PCMCIA Interrupt Register
R/W Configuration Option Register R/W Card Config. and Status Reg. R/W Pin Replacement Register R/W Socket and Copy Register -
R/W R/W R/W R/W R/W R/W R/W R/W W R/W+ R/W
R W -
R/W W+ -
W
ATA Feature Register
R/W ATA Sector Count Register R/W ATA Sector Number Register R/W ATA Cylinder Low Register R/W ATA Cylinder High Register R/W ATA Drive/Head Register W R R W R ATA Command Register ATA Status Register ATA Error Register ATA Device Control Register ATA Drive Address Register
W+ means that the register is writable, but coinciding accesses from the other side (PC) will be corrupted. 4.7.1. Register Descriptions for the F2-16X Registers
4.7.1.1 F2-16X Register Access
The F2-16X PCMCIA control registers ISR, MSR, TIR and PIR are exclusively owned by the F2-16X and may be read and written at any time. An internal I/O access is used to read and write the F2-16X PCMCIA control registers.
4.7.1.2 Mode and Control Register
MSR bit Description 0 ATA Mode bit 0 = PCMCIA ATA mode (reset default if POE# is high) 1 = True IDE mode (reset default if POE# is low) This bit should not be changed by software. When the True-IDE detection enable bit is set in PIR, this bit falls back to 0 if POE# was low at reset time as soon as POE# changes back to high. When the True-IDE detection enable bit in PIR is cleared, this bit is not affected by changes of the POE# pin.
24
FUNCTIONAL DESCRIPTION
MSR bit Description 1 Access Mode bit 0 0 = Memory Mapped access (reset default) 1 = I/O Mapped access 2 Access Mode bit 1 0 = Contiguous I/O address decoding (when I/O mapped access is selected) 1 = Primary/Secondary I/O address decoding (when I/O mapped access is selected) For memory mapped access, this bit must be set to 0. The reset default for this bit is 0. 3 PCMCIA Interrupt Status (PIREQ#), read-only 0 = PCMCIA Interrupt line not active (reset default) 1 = PCMCIA Interrupt line active The PCMCIA Interrupt line is controlled in PIR. 4 Clear Sector Buffer Address Counter, write only, normally reads as 0 0 = Normal Address Counter Operation (reset default) 1 = Clear Address Counter Writing a 1 to this bit also clears the Address Counter Overflow bit in ISR. This bit also captures the "Service Mode" state at power-on reset. When both PWE# and PWAIT# are low at power-on, this bit reads as 1 as long as both PWE# and PWAIT# are low. When at least one of PWE# or PWAIT# goes back high, this bit reverts to the 0 state and stays there. This feature is used in the internal boot ROM to switch to a "Service Mode" where F2-16X boots via the PCMCIA interface. Before the PCMCIA boot is completed, the PWE# or PWAIT# pin should be brought back high so that this bit reads as 0 during normal operation. 5 PCMCIA Reset (PRESET) Status, read only 0 = PCMCIA reset is not active 1 = PCMCIA reset is active PCMCIA reset polarity is high active in PCMCIA mode, low active in True-IDE mode 6 DMA Request in True-IDE mode 0 = DMA Request inactive (low on PINPACK#, reset default) 1 = DMA Request active (high on PINPACK#) The DMA Request bit is automatically reset to the inactive state during a DMA transfer at the beginning of the PIORD# or PIOWR# pulse when the last byte of a sector is read or written. 7 Busy Set Enable on Address Counter Overflow 0 = Busy flag is not affected by an Address Counter overflow (reset default) 1 = Busy flag is set whenever the Address Counter overflows 8 Sector Buffer Access Select 0 = F2-16X accesses Sector Buffer 0, PC accesses Sector Buffer 1 (reset default) 1 = F2-16X accesses Sector Buffer 1, PC accesses Sector Buffer 0 9 DMA Request Driver Enable in True-IDE mode 0 = Driver disabled, PINPACK# pad is tristate (reset default) 1 = Driver enabled, PINPACK# pad is enabled when the drive is selected In PCMCIA I/O mode (non-True-IDE), the PINPACK# driver is always enabled, and the pad performs the "Input Acknowledge" functionality. 10 State at the PINPACK# pad (True-IDE DMARQ), read only 0 = PINPACK# pad is low (DMARQ inactive) 1 = PINPACK# pad is high (DMARQ active)
FUNCTIONAL DESCRIPTION
25
MSR bit Description 11 State at the PREG# pad (True-IDE DMACK#), read only 0 = PREG# is high (DMACK inactive) 1 = PREG# is low (DMACK active) 12..14 15 Reserved PCMCIA CIS Write Permission 0 = CIS (in Attribute Memory) is not writable from the host (reset default) 1 = CIS (in Attribute Memory) is writable from the host
At boot time, the Hyperstone F2-16X software must read out the ATA Mode bit and initialize the two access mode bits to memory-mapped mode for PCMCIA ATA mode and to Primary I/O mode in True IDE mode. The configuration index in the PCMCIA Configuration Option Register must be initialized to zero for PCMCIA ATA mode and to nonzero for True IDE mode.
4.7.1.3 TIR bit 0 True-IDE Mode Register Description PDIAG (signal is on PSTSCHG#) 0 = PSTSCHG# pad is tristate (reset default) 1 = pull PSTSCHG# pad low When read, this bit reflects the PSTSCHG# pad's state (low reads as 1). 1 PDASP (signal is on PSPKR#) 0 = PSPKR# pad is tristate (reset default) 1 = pull PSPKR# pad low When read, this bit reflects the PSPKR# pad's state (low reads as 1). 2 Drive Select 0 = Drive selects as Master (reset default if PCSEL# is low) 1 = Drive selects as Slave (reset default if PCSEL# is high) This bit must be initialized to 0 for the PCMCIA mode. 3 Drive 1 Status Register Read Enable 0 = Disable reading drive 1 status register (reset default) 1 = Enable reading drive 1 status register This bit must be set in True IDE mode when our drive is configured as master with no slave present. 4 8 Bit Data Register Access Enable 0 = True-IDE data register access is 16 bit per transfer (reset default) 1 = True-IDE data register access is 8 bit per transfer 5 Multiple Controllers Master/Slave Select 0 = Single controller, or master with multiple controllers (reset default) 1 = Slave with multiple controllers 6 BUSRQ Line Control 0 = BUSRQ line is tristate, with pull-up on master (reset default) 1 = BUSRQ line is driven low When read, this bit reflects the BUSRQ pad's state (low reads as 1).
26
FUNCTIONAL DESCRIPTION
When multiple controllers are connected to the PCMCIA bus, exactly one of these must be the master, all others must be slave. The PCMCIA lines of a controller are driven if either 4.7.1.4
a controller is master, and the BUSRQ line is high, or a controller is slave, and pulls the BUSRQ line low.
Interrupt Status Register
When any of the ISR bits is set, the processor's INT1 or INT2 interrupts are activated. The interrupt service routine should read ISR, clear the bits it found set, and act upon them. A bit in ISR is cleared by writing a 1 bit into the appropriate bit position, writing a 0 bit to a bit position does not affect the bit's value.
ISR bit 0 Description Configuration Register Write Interrupt 1 = The PCMCIA Configuration Option Register was written by the PCMCIA host. 1 Command Register Write Interrupt 1 = The ATA Command Register was written by the PCMCIA host. The Command Register Write causes the Busy flag to be set. 2 Address Counter Overflow Interrupt 1 = The Sector Buffer Address Counter passed the end of the sector buffer. This bit is also cleared by writing a 1 into MSR bit 4. The Address Counter overflow causes the Busy flag to be set if this is enabled in MSR bit 7. 3 PCMCIA Soft Reset was set Interrupt 1 = The Soft Reset bit was set in the ATA Device Control Register or in the PCMCIA Configuration Option Register. The Soft Reset via the ATA Device Control Register causes the Busy flag to be set. 4 PCMCIA Soft Reset was cleared Interrupt 1 = The Soft Reset bit was cleared in the ATA Device Control Register or in the PCMCIA Configuration Option Register. 5 PCMCIA Power Down Request Interrupt 1 = The Power Down Request bit was set in the PCMCIA Card Configuration and Status Register 6 PCMCIA Reset (PRESET) was set Interrupt 1 = The PCMCIA Reset line was activated. 7 PCMCIA Reset (PRESET) was cleared Interrupt 1 = The PCMCIA Reset line was deactivated. 8..12 Flash Ready Interrupts 0..4 1 = Rising edge detected on address line A9..A13.
Any bit set in positions 0..7 of ISR activates interrupt INT1. Any bit set in positions 8..12 of ISR activates interrupt INT2.
FUNCTIONAL DESCRIPTION
27
4.7.1.5 PIR bit 0
PCMCIA Interrupt Register Description Set PCMCIA Interrupt Request to the PCMCIA host (write only) 0 = No operation 1 = The PCMCIA Interrupt line is set. Both the PCMCIA Interrupt line and the Interrupt bit in the PCMCIA Card Configuration and Status Register are reset when: - the ATA Status Register is read by the PCMCIA host - the ATA Command Register is written by the PCMCIA host - the PCMCIA Soft Reset was set Interrupt bit in ISR is set - and on a power-on reset.
1
Clear PCMCIA Interrupt Request to the PCMCIA host (write only) 0 = No operation 1 = The PCMCIA Interrupt line is reset.
2
Set Interrupt bit in the PCMCIA Card Configuration and Status Register (write only) 0 = No operation 1 = The Interrupt bit in the PCMCIA Card Configuration and Status Register is set.
3
Clear Interrupt bit in the PCMCIA Card Configuration and Status Register (write only) 0 = No operation 1 = The Interrupt bit in the PCMCIA Card Configuration and Status Register is cleared.
4..5 6
Unused Set True-IDE Detection Enable 0 = No operation 1 = The True-IDE detection enable bit is set. The True-IDE detection enable bit is set after power-on reset. As long as this bit is set, the True-IDE bit in MSR is reset to 0 as soon as a high (inactive) level is recognized on the POE# pin. When this bit is not reset, POE# activity does not affect the MSR TrueIDE bit.
7
Clear True-IDE Detection Enable 0 = No operation 1 = The True-IDE detection enable bit is cleared.
4.7.2. Register Descriptions for the PCMCIA Registers
4.7.2.1 PCMCIA Configuration Register Access
The PCMCIA Configuration Registers can be accessed via internal I/O accesses by the F216X and via PCMCIA memory accesses by the PCMCIA host. Write access to these registers is guarded by the Busy flag: when Busy is set, the F2-16X may write the PCMCIA Configuration Registers, when Busy is clear, the PCMCIA host may write these registers. For the PCMCIA host access to the PCMCIA configuration registers, an Attribute Memory read or write access is needed with an address of 20016, 20216, 20416 or 20616. These addresses select C1, C2, C3 and C4, respectively.
28
FUNCTIONAL DESCRIPTION
4.7.2.2 C1 bit 5..0 6
Configuration Option Register Description Configuration Index PCMCIA Interrupt Mode Select 0 = Pulse Mode Interrupts 1 = Level Mode Interrupts
7
PCMCIA Soft Reset 0 = Normal operation 1 = Software Reset
Any write access by the PCMCIA host to this register causes a Configuration Register Write Interrupt. The F2-16X disables I/O accesses from the PCMCIA interface as long as the Configuration Index is zero. Prior to enabling the I/O interface in MSR, a Configuration Index unequal to zero must be written. This is done by the host (in PCMCIA mode) or must be done by the F2-16X (in True-IDE mode). When the PCMCIA Soft Reset bit is changed, a PCMCIA Soft Reset interrupt is generated.
4.7.2.3 C2 bit 0 1 Card Configuration and Status Register Description Reserved (0) PCMCIA Interrupt (read only) This bit is controlled by bits 0 and 2 of PIR. 2 PCMCIA Power Down Request 0 = Normal Operation 1 = Enter Power Down mode. 3 PCMCIA Audio This bit is unused in F2-16X and should be set to 0. 4 5 Reserved (0) PCMCIA IOis8 This bit should be set to 0 by the F2-16X since 16 bit I/O is possible. 6 Signal State Change 0 = State Changes (the Changed bit) should not be reported through PSTSCHG# 1 = State Changes are reported through the PSTSCHG# signal. 7 Changed (read only) This bit represents the logical or of bits 4 to 7 of the Pin Replacement Register.
When the PCMCIA Power Down Request bit is set, a PCMCIA Power Down Request interrupt is generated.
4.7.2.4 Pin Replacement Register
All PCMCIA Pin Replacement Register bits can be written by the F2-16X. In order to conform to the PCMCIA protocol, every time a bit from bits 0 to 3 is set, the corresponding bit in bits 4 to 7 must be set by the F2-16X. This can be done by a read-modify-write cycle
FUNCTIONAL DESCRIPTION
29
since write accesses to the Pin Replacement Register are guarded by the Busy signal. When a bit from bits 0 to 3 is reset, the corresponding bit in bits 4..7 must not be changed. The PCMCIA host has no write access to bits 0 to 3. Bits 4 to 7 can be written by the PCMCIA host through a write mask in the corresponding bit of bits 0 to 3: for example, if the PCMCIA host performs a write access to the Pin Replacement Register with data bits 1 and 2 set, bits 5 and 6 of the Pin Replacement Register are written with the data bits 5 and 6 from the PCMCIA host, and bits 0 to 3, 4 and 7 are not changed by this write access.
C3 bit 0 Description Write Protect This bit is used to generate the WP signal (PIOIS16# pin) in memory-mapped mode. 1 2 3 4 5 6 7 4.7.2.5 C4 bit 3..0 6..4 7 Ready/-Busy Battery Voltage Detect 2 (set to 0 when no battery is there) Battery Voltage Detect 1 (set to 0 when no battery is there) Changed Write Protect Changed Ready/-Busy Changed Battery Voltage Detect 2 Changed Battery Voltage Detect 1 Socket and Copy Register Description Socket Number Copy Number Reserved (0)
4.7.3. Register Descriptions for the ATA Task File Registers
4.7.3.1 ATA Task File Register Access
The ATA Task File Registers can be accessed by the F2-16X using internal I/O accesses and by the PCMCIA host using I/O or memory accesses on the PCMCIA interface. See section 4.8 Register and Sector Buffer Access Modes for details.
4.7.3.2 A01 bit 7..0 4.7.3.3 A02 bit 7..0 ATA Feature Register Description Command Specific ATA Sector Count Register Description Sector Count for read or write operation. Sector Count 0 means 256 sectors.
30
FUNCTIONAL DESCRIPTION
4.7.3.4 A03 bit 7..0
ATA Sector Number Register Description Sector Number for the next command, range 1 to max. number of sectors per track. LBA bits 7..0 in LBA addressing mode. ATA Cylinder Low Register Description Bits 7..0 of the starting cylinder number for the next command. LBA bits 15..8 in LBA addressing mode. ATA Cylinder High Register Description Bits 15..8 of the starting cylinder number for the next command. LBA bits 23..16 in LBA addressing mode. ATA Drive/Head Register Description Head number to select for the next command (0..15). LBA bits 27..24 in LBA mode. Drive 0 select (0) or Drive 1 select (1) Reserved (1) Addressing Mode select 0 = addressing is by Cylinder/Head/Sector (CHS mode) 1 = addressing is by LBA mode
4.7.3.5 A04 bit 7..0
4.7.3.6 A05 bit 7..0
4.7.3.7 A06 bit 3..0 4 5 6
7 4.7.3.8
Reserved (1) ATA Command Register
A PCMCIA write access to the ATA Command Register causes the Busy flag to be set and generates a Command Register Write Interrupt.
A07 bit 7..0 4.7.3.9 Description Command Code for the next command to be executed. ATA Status Register, ATA Alternate Status Register
The ATA Status Register and the ATA Alternate Status Register carry the same information. The only difference is, reading the ATA Status Register implies an interrupt acknowledge and resets the PCMCIA Interrupt line while reading the ATA Alternate Status Register does not.
FUNCTIONAL DESCRIPTION
31
A00 bit 0 1 2 3 4 5 6 7
Description ERR (Error). An error occurred during command execution, further information can be found in the Error Register IDX (Index). CORR (Corrected Data). A correctable data error occurred and the data has been corrected. DRQ (Data Request). The drive is ready to transfer data. This bit is cleared when a host Data Register access causes an Address Counter overflow. DSC (Drive Seek Complete). DWF (Drive Write Fault) DRDY (Drive Ready). The drive is ready to accept a command. BSY (Busy). This bit indicates that the drive has access to the ATA Registers. When any ATA register is read by the PCMCIA host, the Status Register content is returned.
The F2-16X hardware sets the Busy flag on any of the following events: power-up reset any PCMCIA write access to the ATA Command Register the Soft Reset bit in the ATA Device Control Register is being set sector buffer address counter overflow when MSR bit 7 is set.
4.7.3.10 ATA Error Register A08 bit 7..0 Description Status from the last command, valid when the ERR bit in the ATA Status Register is set. Diagnostic code from Execute Drive Diagnostics command.
4.7.3.11 ATA Device Control Register A10 bit 0 1 Description Reserved (0) nIEN (negated Interrupt Enable). This bit is initialized to 0 on power-on reset and on PCMCIA reset assertion. 0 = Interrupt is enabled 1 = Interrupt is disabled 2 3 SRST (Soft Reset). This bit is initialized to 0 on reset. Reserved (1)
The PCMCIA Interrupt line is used as Ready/-Busy output in memory-mapped mode. In I/O mode, the interrupt line state is determined by the PCMCIA Interrupt bit that is set or reset by PIR bits 0 and 1 and queried in MSR bit 5. In PCMCIA I/O mode, the interrupt line is always driven (active high) according to the PCMCIA Interrupt bit. In True-IDE mode, the interrupt line is driven (active low) according to the PCMCIA Interrupt bit when the drive is selected (bit 4 in the ATA Drive/Head Register equals bit 2 in TIR), else the interrupt line is tristate. When the SRST bit is being set by the PCMCIA host, the Busy flag is set and a PCMCIA Soft Reset was set Interrupt is generated. When this bit is being cleared by the PCMCIA host, a PCMCIA Soft Reset was cleared Interrupt is generated.
32
FUNCTIONAL DESCRIPTION
4.7.3.12 ATA Drive Address Register A09 bit 0 1 5..2 6 7 Description nDS0 (negated Drive Select 0). Low when drive 0 is selected and active. nDS1 (negated Drive Select 1). Low when drive 1 is selected and active. nHS3..nHS0 (negated head select). Contains the negated binary address of the currently selected head. nWGT (negated Write Gate). Low when a write to the disk is in progress. HiZ
The ATA Drive Address Register is only available in PCMCIA memory or I/O modes. In True-IDE mode, the F2-16X controller does not respond to ATA Drive Address Register accesses.
4.8. Register and Sector Buffer Access Modes
The Sector Buffer (512 byte) and ATA Task File Registers are available in both memorymapped and I/O access mode in the PCMCIA Common Memory area. 4.8.1. Access Modes in PCMCIA memory-mapped mode For common memory access (Sector Buffer and ATA Task File), the access signals are:
PREG# x 1 1 1 1 PCE2# PCE1# 1 1 1 0 0 1 0 0 1 0 PA0 x 0 1 x x Access WE/OE WE/OE WE/OE WE/OE Description Standby Byte access (even byte), data on PD(7..0) Byte access (odd byte), data on PD(7..0) Byte access (odd byte), data on PD(15..8) Word access, data on PD(15..0)
Word accesses are permitted for Sector Buffer (Data Register) accesses as well as for ATA Task File Register accesses. On word accesses to the ATA Task File Registers, the even and odd addresses are accessed simultaneously. The Sector Buffer (Data Register) and ATA Task File Register addresses in memorymapped mode are given in the following table.
PA10 0 0 0 0 0 0 0 0 0 0 PA9..4 x x x x x x x x x x PA3 0 0 0 0 0 0 0 0 0 1 PA2 0 0 0 0 0 1 1 1 1 0 PA1 0 0 0 1 1 0 0 1 1 0 PA0 even word odd even odd even odd even odd even Read (OE) Write (WE) Data Register, byte access Data Register, byte acc. Data Register, word acc. Error Register Sector Count Sector Number Cylinder Low Register Cylinder High Register Drive/Head Register Status Register Duplicate Data, even byte Data Register, word acc. Feature Register Sector Count Sector Number Cylinder Low Register Cylinder High Register Drive/Head Register Command Register Duplicate Data, even byte
FUNCTIONAL DESCRIPTION
33
PA10 0 0 0 0 0 1 1 1
PA9..4 x x x x x x x x
PA3 1 1 1 1 1 x x x
PA2 0 0 1 1 1 x x x
PA1 0 0 0 1 1 x x x
PA0 odd word odd even odd even odd word
Read (OE) Duplicate Data, odd byte Duplicate Data Duplicate Error Register Alternate Status Register Drive Address Register Data Register, even byte Data Register, odd byte Data Register
Write (WE) Duplicate Data, odd byte Duplicate Data Duplicate Error Register Device Control Register Data Register, even byte Data Register, odd byte Data Register
For Attribute Memory (CIS and PCMCIA Configuration Registers), only even addresses are valid. The access signals are:
PREG# x 0 0 0 0 PCE2# PCE1# 1 1 1 0 0 1 0 0 1 0 PA0 x 0 1 x x Access WE/OE WE/OE WE/OE WE/OE Description Standby Byte access (even byte), data on PD(7..0) not valid not valid Word access, even byte data on PD(7..0)
The Attribute Memory (Card Information Structure) and PCMCIA Configuration Register addresses in memory-mapped mode are given in the following table.
PA9 0 1 1 1 1 PA8..3 PA2 PA1 PA0 even 0 1 0 1 even even even even Description 256 bytes Card Information Structure PCMCIA Configuration Option Register (C1) PCMCIA Card Configuration and Status Register (C2) PCMCIA Pin Replacement Register (C3) PCMCIA Socket and Copy Register (C4) 8 bit address x x x x 0 0 1 1
Write accesses to the Card Information Structure are only possible if the PCMCIA CIS Write Permission bit in MSR is set. 4.8.2. Access Modes in PCMCIA I/O mode In I/O mode, common and attribute memory access signals are:
PREG# x 0 0 0 0 PCE2# PCE1# 1 1 1 0 0 1 0 0 1 0 PA0 x 0 1 x x Access Description Standby
IOWR/RD Byte access (even byte), data on PD(7..0) IOWR/RD Byte access (odd byte), data on PD(7..0) IOWR/RD Byte access (odd byte), data on PD(15..8) IOWR/RD Word access, data on PD(15..0)
34
FUNCTIONAL DESCRIPTION
PREG# 0
PCE2# PCE1# x x
PA0 x
Access WE/OE
Description Attribute Memory access, see memory-mapped mode
Word accesses are permitted for Sector Buffer (Data Register) accesses as well as for ATA Task File Register accesses. On word accesses to the ATA Task File Registers, the even and odd addresses are accessed simultaneously. The Sector Buffer (Data Register) and ATA Task File Register addresses in Contiguous I/O mode are given in the following table.
PA3 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 PA2 0 0 0 0 0 1 1 1 1 0 0 0 1 1 1 PA1 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 PA0 even word odd even odd even odd even odd even odd word odd even odd Read (IORD) Data Register, byte access Data Register, word access Error Register Sector Count Sector Number Cylinder Low Register Cylinder High Register Drive/Head Register Status Register Duplicate Data, even byte Duplicate Data, odd byte Duplicate Data Duplicate Error Register Alternate Status Register Drive Address Register Write (IOWR) Data Register, byte access Data Register, word access Feature Register Sector Count Sector Number Cylinder Low Register Cylinder High Register Drive/Head Register Command Register Duplicate Data, even byte Duplicate Data, odd byte Duplicate Data Duplicate Error Register Device Control Register -
The Sector Buffer (Data Register) and ATA Task File Register addresses in Primary or Secondary I/O mode are given in the following table.
PA9 0 0 0 0 0 0 0 0 0 1 1 PA2 0 0 0 0 0 1 1 1 1 1 1 PA1 0 0 0 1 1 0 0 1 1 1 1 PA0 even word odd even odd even odd even odd even odd Read (IORD) Data Register, byte access Data Register, word access Error Register Sector Count Sector Number Cylinder Low Register Cylinder High Register Drive/Head Register Status Register Alternate Status Register Drive Address Register Write (IOWR) Data Register, byte access Data Register, word access Feature Register Sector Count Sector Number Cylinder Low Register Cylinder High Register Drive/Head Register Command Register Device Control Register -
FUNCTIONAL DESCRIPTION
35
4.8.3. Access Modes in True-IDE mode In True-IDE mode, only common memory (Sector Buffer and ATA Task File) is addressable. The access signals are:
PREG# x x x x PCE2# PCE1# 1 1 0 0 1 0 1 0 Access Description Standby
IOWR/RD ATA Command block access (Cmd in table below) IOWR/RD ATA Control block access (Ctrl in table below) IOWR/RD not valid
A word access is valid only for the Sector Buffer (Data Register) access. The Sector Buffer (Data Register) and ATA Task File Register addresses in True-IDE Primary or Secondary I/O mode are given in the following table.
Block Cmd Cmd Cmd Cmd Cmd Cmd Cmd Cmd Ctrl PA2 0 0 0 0 1 1 1 1 1 PA1 0 0 1 1 0 0 1 1 1 PA0 0 1 0 1 0 1 0 1 0 Read (IORD) Data Register, word access Error Register Sector Count Sector Number Cylinder Low Register Cylinder High Register Drive/Head Register Status Register Alternate Status Register Write (IOWR) Data Register, word access Feature Register Sector Count Sector Number Cylinder Low Register Cylinder High Register Drive/Head Register Command Register Device Control Register
The Drive Address Register is not available in True-IDE mode.
4.9. Hyperstone Sector Buffer Access
The sector buffers and the attribute memory are available on the Hyperstone side in the IRAM access space, starting at C800 000016. There are two sector buffers of 528 bytes (132 words of 32 bits), and a 256 byte attribute memory. Read accesses to these memories are unrestricted, write accesses must always be in 32 bit units (byte or halfword write accesses are not allowed). The selection which of the sector buffers are accessed from the Hyperstone side and from the host side depends on the Sector Buffer Select bit in MCR, and on the Busy state. The access modes are detailed in the following table. When Busy is 0, the host side (PCMCIA) always has access to sector buffer SB0 when MSR(8) is 1, and to sector buffer SB1 when MSR(8) is 0. The 256 byte attribute memory is mapped to 256 words in this address range, with the 8 bit data in bits 31..24 of these words.
36
FUNCTIONAL DESCRIPTION
Busy
Hyperstone Address Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Hy Access MSR(8)=0 SB0
Hy Access MSR(8)=1 SB1 SB1 SB0 SB0 SB1
0 0 0 0 1 1 1 1 1
0 X x 1 0 0 0 0 1
x x x x x x x x x
0 x 1 x 0 0 1 1 x
x x x x x x x x x
x x x x x x x x x
0 1 x x 0 1 0 1 x x x x x x x x x x x x x
528 byte x x x x x x x x x x x x x x x x x x
SB0 SB1
528 byte 528 byte 528 byte 528 byte 256 byte 0 0
Attribute Memory
4.10. Internal ROM
The F2-16X has 8 Kbytes of internal ROM at address D000 000016 with a wraparound modulo 8 Kbytes up to DFFF FFFF16. When the interrupt 4 input of the F2-16X is low (or open) at reset, the reset trap begins executing the internal boot ROM code at DFFF FFF816. The internal ROM present on the F2-16X performs the following actions on reset when booting is done from ROM:

The F2-16X processor is initialized. IO(3) is switched to output driving 0 (for Samsung Flashes) or 1 (for Hitachi Flashes), FCR bit 7 (Flash Select) is initialized according to the detected Flash type. After 50 s delay for the stabilization of the voltage regulator, all Flashes are deselected and IO(2) (Flash Write Protect) is switched to output driving 1 so that Flash access is possible. The Busy flag is set in the ATA Status Register. The PCMCIA and ATA Registers are initialized to allow a PCMCIA boot if a power-on reset is detected. If the PWE# and PWAIT# pins were low at reset and still are, the F2-16X tries to boot from PCMCIA. Else, the F2-16X tries to boot from Flash 0. This involves a search of the Anchor Block and a load of the Main Program and Overlay sectors. If the Anchor Block is not found or if there is an uncorrectable error when loading the program, the F2-16X falls back to booting from PCMCIA. If the Anchor Block is found, a copy is stored in the sector buffer SB1 Then, a pre-boot routine at offset 01FC16 in SB1 is called. After return, the F2-16X processor proceeds to load the Program and Overlay sectors from Flash 0 using the Anchor Block information in sector buffer SB1. For the PCMCIA boot, the F2-16X determines the device ID of flash chip 0 and stores this information in the cylinder high and low registers. Then, the F2-16X writes B816 into the ATA Error register and sets DRDY, DSC and ERR in the ATA Status register. The boot software on the host must then respond by writing the number of sectors (512 bytes) to boot into the ATA Sector Count register and 8016 into the ATA Command register. The F2-16X then reads the specified number of sectors by setting DRDY, DRQ and DSC in the ATA Status register. The downloaded code is put into IRAM starting at address C000 000016.

ELECTRICAL SPECIFICATIONS
37
5. Electrical Specifications
5.1. DC Characteristics
5.1.1. Absolute Maximum Ratings Case temperature TC under Bias: extended temperature range on request Storage Temperature: Voltage on any Pin with respect to ground: 5.1.2. D.C. Parameters Supply Voltage VCC_P and VCC_R: Supply Voltage VCC_F: Supply Voltage VCC_C: Case Temperature TCASE:
Symbol VIL VIH VOL VOH ICC Parameter Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage Operating Current, VCC_R=5.0V Sleep mode Operating, 20 MHz Operating, 40 MHz ICC Operating Current, VCC_R=3.3V Sleep mode Operating, 20 MHz Operating, 40 MHz 0.2 ** ** mA mA mA 0.2 ** ** mA mA mA 2.4 Min -0.3 2.0
0C to +85C -65C to +150C -0.5V to VCC + 0.5V
5V 0.25V or 3.3V 0.30V 3.3V 0.30V 2.5V 0.25V 0C to +85C
Max +0.8 VCC+0.3 0.45 Units V V V V at 4mA at 1mA Notes
ILI ILO CI/O
Input Leakage Current Output Leakage Current Input/output Capacitance
10 10 10
A A pF
Table 2: DC Characteristics
38
ELECTRICAL SPECIFICATIONS
5.2. AC Characteristics
The AC Characteristics reference the timing diagrams of the PCMCIA PC Card Standard and the symbols in these timing diagrams. The AC characteristics are valid for a supply voltage VCC of 5V 10% or 3.3V 5%. 5.2.1. Attribute Memory Read and Write AC Characteristics
Symbol tcR ta(A) ta(CE) ta(OE) tdis(CE) tdis(OE) ten(CE) ten(OE) tv(A) tsu(A) th(A) tsu(CE) th(CE) tcW tw(WE) tsu(A-WEH) tsu(CE-WEH) tsu(D-WEH) th(D) tdis(WE) ten(WE) tsu(OE-WE) th(OE-WE) Parameter Read cycle time Address access time Card Enable access time Output Enable access time Output disable time from CE Output disable time from OE Output enable time from CE Output enable time from OE Data valid time from address change Address setup time Address hold time Card Enable setup time Card Enable hold time Write cycle time Write pulse time Address setup time for WE Card Enable setup time for WE Data setup time for WE Data hold time Output disable time from WE Output enable time from WE Output Enable setup time for WE Output Enable hold time from WE 5 10 10 5 5 0 30 20 0 20 250 150 180 180 80 30 100 Min 250 250 250 125 100 100 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 3: Attribute Memory Read and Write AC Characteristics
ELECTRICAL SPECIFICATIONS
39
5.2.2. Common Memory Read and Write AC Characteristics
Symbol tcR ta(A) ta(CE) ta(OE) tdis(CE) tdis(OE) ten(CE) ten(OE) tv(A) tsu(A) th(A) tsu(CE) th(CE) tcW tw(WE) tsu(A-WEH) tsu(CE-WEH) tsu(D-WEH) th(D) trec(WE) tdis(WE) ten(WE) tsu(OE-WE) th(OE-WE) Parameter Read cycle time Address access time Card Enable access time Output Enable access time Output disable time from CE Output disable time from OE Output enable time from CE Output enable time from OE Data valid time from address change Address setup time Address hold time Card Enable setup time Card Enable hold time Write cycle time Write pulse time Address setup time for WE Card Enable setup time for WE Data setup time for WE Data hold time Write recover time Output disable time from WE Output enable time from WE Output Enable setup time for WE Output Enable hold time from WE 5 10 10 5 5 0 20 20 0 20 150 80 100 100 50 20 20 75 Min 150 150 150 75 75 75 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 4: Common memory Read and Write AC Characteristics
40
ELECTRICAL SPECIFICATIONS
5.2.3. I/O Access Read and Write AC Characteristics
Symbol td(IORD) th(IORD) tw(IORD) tsuA(IORD) thA(IORD) tsuCE(IORD) thCE(IORD) tsuREG(IORD) thREG(IORD) tdfINP(IORD) tdrINP(IORD) tdfIO16(IORD) tdrIO16(IORD) tsu(IOWR) th(IOWR) tw(IOWR) tsuA(IOWR) thA(IOWR) tsuCE(IOWR) thCE(IOWR) tsuREG(IOWR) thREG(IOWR) Parameter Data delay after IORD Data hold following IORD IORD pulse width Address setup time for IORD Address hold time from IORD Card Enable setup time for IORD Card Enable hold time from IORD REG setup time for IORD REG hold time from IORD INPACK delay falling from IORD INPACK delay rising from IORD IOIS16 delay falling from address IOIS16 delay rising from address Data setup time for IOWR Data hold time from IOWR IOWR pulse width Address setup time for IOWR Address hold time from IOWR Card Enable setup time for IOWR Card Enable hold time from IOWR REG setup time for IOWR REG hold time from IOWR 60 30 165 70 20 5 20 5 0 0 165 70 20 5 20 5 0 0 45 45 35 35 Min Max 100 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 5: I/O Access Read and Write AC Characteristics
ELECTRICAL SPECIFICATIONS
41
5.2.4. True-IDE Mode I/O Access Read and Write AC Characteristics
Symbol tcR tsuA thA tw trec tsuD(IORD) thD(IORD) tdis(IORD) tsuD(IOWR) thD(IOWR) Parameter Cycle time Address setup time for IORD/IOWR Address hold time from IORD/IOWR IORD/IOWR pulse width IORD/IOWR recovery time Data setup time for IORD Data hold following IORD Output disable time from IORD Data setup time for IOWR Data hold following IOWR 20 10 Min 120 25 10 70 25 20 5 30 Max Units ns ns ns ns ns ns ns ns ns ns
Table 6: True-IDE Mode I/O Access Read and Write AC Characteristics
5.2.5. Flash Memory Interface AC Characteristics, Samsung Type The AC Characteristics for the flash memory interface are based on a F2-16X processor clock speed of 20 MHz.
Symbol tCLS tCLH tCS tCH tWP tALS tALH tDS tDH tWC tWH tRP tRC tREA tREH tCEH tWHR Parameter CLE setup time CLE hold time CE setup time CE hold time WE pulse width ALE setup time ALE hold time Data Setup time Data hold time Write cycle time WE high hold time RE pulse width Read cycle time RE access time RE high hold time CE high hold time WE high to RE low Min 50 20 50 50 25 50 20 25 20 50 20 30 50 35 15 200 100 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 7: AC Characteristics for Samsung Type flash memory
42
ELECTRICAL SPECIFICATIONS
5.2.6. Flash Memory Interface AC Characteristics, Hitachi Type The AC Characteristics for the flash memory interface are based on a F2-16X processor clock speed of 18 MHz.
Symbol tCWC tSCC tWP tWPH tAS tAH tDS tDH tSP tSPL tCDS tCDH tCPH tDS tDH Parameter Write cycle time Serial clock cycle time Write pulse time Write pulse high time Address setup time Address hold time Data setup time for WE Data hold time from WE SC pulse width SC pulse low time CDE setup time for WE CDE hold time for WE CE pulse high time Data setup time for SC Data hold time from SC Min 150 50 90 50 120 20 120 20 20 20 20 20 200 20 30 Max Units Ns Ns Ns Ns Ns Ns Ns Ns Ns Ns Ns Ns Ns Ns ns
Table 8: AC Characteristics for Hitachi Type flash memory
43
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Hyperstone AG Am Seerhein 8 D-78467 Konstanz Germany Phone +49 - 7531 - 98030 Fax +49 - 7531 - 51725 E-Mail info@hyperstone.de
http://www.hyperstone.com

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